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sy89200u ultra-precision 1:8 lvds fanout buffer with three 1/2/4 clock divider output banks precision edge is a register ed trademark of micrel, inc mlf and microleadframe are registered trademark of amkor technology. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com april 2010 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 general description the sy89200u is a 2.5v precision, high-speed, integrated clock divider and lvds fanout buffer capable of handling clocks up to 1.5ghz. optimized for communications applications, the three independently controlled output banks are phase matched and can be configured for pass through (1), 2 or 4 divider ratios. the differential input includes micrel?s unique, 3-pin input termination architecture that allows the user to interface to any differential signal path. the low-skew, low-jitter outputs are lvds-compatible with extremely fast rise/fall times guaranteed to be less than 150ps. the en (enable) input guarantees that the 1, 2 and 4 outputs will start from the same state without any runt pulse after an asynchronous master rest (mr) is asserted. this is accomplished by enabling the outputs after a four- clock delay to allow the counters to synchronize. the sy89200u is part of micrel?s precision edge ? product family. datasheets and support documentation can be found on micrel?s web site at: www.micrel.com . functional block diagram precision edge ? features ? three low-skew lvds output banks with programmable 1, 2 and 4 divider options ? three independently programmable output banks ? guaranteed ac performance over temperature and voltage: ? accepts a clock frequency up to 1.5ghz ? <900ps in-to-out propagation delay ? <150ps rise/fall time ? <50ps bank-to-bank phase offset ? ultra-low jitter design: ? <1ps rms random jitter ? <10ps pp total jitter (clock) ? patent-pending input termination and vt pin accepts dc- and ac-coupled inputs (cml, pecl, lvds) ? lvds-compatible outputs ? cmos/ttl-compatible output enable (en) and divider select control ? 2.5v 5% power supply ? ?40c to +85c temperature range ? available in 32-pin (5mm x 5mm) mlf ? package applications ? all sonet/sd applications ? all fibre channel applications ? all gigabit ethernet applications
micrel, inc. sy89200u april 2010 2 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type temperature range package marking lead finish sy89200umi mlf-32 industrial sy89200u sn-pb sy89200umitr (2) mlf-32 industrial sy89200u sn-pb SY89200UMG mlf-32 industrial sy89200u with pb-free bar-line indicator pb-free nipdau SY89200UMGtr (2) mlf-32 industrial sy89200u with pb-free bar-line indicator pb-free nipdau note: 1. contact factory for die availability. dice are guaranteed at ta = 25c, dc electricals only. 2. tape and reel. pin configuration 32-pin mlf ? (mlf-32)
micrel, inc. sy89200u april 2010 3 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 3, 6 in, /in differential input: this input pair is the differ ential signal input to the device. this input accepts ac- or dc-coupled signals as sma ll as 100mv. the input pair internally terminates to a vt pin through 50 ? . note that these inputs will default to an indeterminate state if left open. please refer to the ?input in terface applications? section for more details. 2 7 8 divsel1 divsel2 divsel3 single-ended inputs: these ttl/cmos inputs select the device ratio for each of the three banks of outputs. note that each of th ese inputs is internally connected to a 25k ? pull-up resistor and will default to logic h igh state if left open. the input-switching threshold is v cc /2. 4 vt input termination center-tap: ea ch side of the differential input pair terminates to the vt pin. the vt pin provides a center-tap to a termination network for maximum interface flexibility. see ?input interface app lications? section for more details. 5 vref-ac reference voltage: this output biases to v cc -1.2v. it is used for ac -coupling inputs in and /in. for ac-coupled applications, connect vref-ac directly to the vt pin. bypass with 0.01f low esr capacitor to v cc . maximum sink/source capability is 0.5ma. 9 en single-ended input: this ttl/cmos input dis able and enable the q0 ? q7 outputs. this input is internally connected to a 25k ? pull-up resistor and will default to logic high state if left open. the input-switching threshold is v cc /2. for the input enable and disable functional description, refer to figures 2a through 2c. 30, 29, 28, 27, 26, 25, 24, 23 q0, /q0, /q1, /q1, q2, /q2 q3, /q3 bank 1 lvds differential output pairs contro lled by divsel1: low q0 ? q3 = 1 high, q0 ? q3 = 2. unused output pairs should be terminated with 100 ? across the differential pair. 16, 15, 14, 13, 12, 11 q4, /q4, q5, /q5, q6, /q6 bank 2 lvds differential output pairs contro lled by divsel2: low q4 ? q6 = 2 high, q4 ? q6 = 2. unused output pairs should be terminated with 100 ? across the differential pair. 18, 17 q7, /q7 bank 3 lvds differential output pairs contro lled by divsel3: low q7 = 2 high. q7 = 2. unused output pairs should be terminated with 100 ? across the differential pair. 32 /mr single-ended input: this ttl/cmos-compatible master reset function asynchronously sets q0 ? q7 outputs low, /q0 ? /q7 outputs h igh, and holds them in that state as long as /mr remains low. this input is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. the input-switching threshold is v cc /2. 10, 19, 22, 31 vcc positive power supply. bypa ss with 0.1f||0.01f low esr capacitors. 1, 20, 21 gnd exposed ground and exposed pad must be connected to the same gnd plane on the board. truth table /mr (1) en (2,3) divsel1 divsel2 divsel3 q0 ? q3 q4 ? q6 q7 0 x x x x 0 0 0 1 0 x x x 0 0 0 1 1 0 0 0 1 2 2 1 1 1 1 1 2 4 4 notes: 1. /mr asynchronously forces q0 ? q7 low (/q0 ? /q7 high). 2. en forces q0 ? q7 low between 2 and 6 input clock cycles after the falling edge of en. refer to ?timing diagram? section. 3. en synchronously enables the outputs between two and six input cl ock cycles after the rising edge of en. refer to ?timing di agram? section.
micrel, inc. sy89200u april 2010 4 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ).................................... ?0.5v to +4.0v input voltage (v in ) ............................................ ?0.5v to v cc termination current (3) source or sink current on v t .............................100ma output current (3) source or sink current on in, /in ........................50ma v ref-ac current (3) source or sink current on v ref-ac .........................2ma lead temperature (solderi ng, 20 sec.).................... +260c storage temperature (t s ) .........................?65c to +150c operating ratings (2) supply voltage (v cc )............................ +2.375v to +2.625v ambient temperature (t a ) .......................... ?40c to +85c package thermal resistance (4) mlf ? ( ja ) still-ai r .........................................................35c/w mlf ? ( jb ) junction ?to- board ...................................... 20c/w dc electrical characteristics t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 2.5 2.625 v i cc power supply current no load, max. v cc , note 6 350 ma r diff_in differential input resistance (in-to-/in) 80 100 120 ? r in input resistance (in-to-v t , /in-to-v t ) 40 50 60 ? v ih input high voltage; (in, /in) 1.2 v cc v v il input low voltage; (in, /in) 0 v ih -0.1 v v in input voltage swing; (in, /in) see figure 1a. 0.1 v cc v v diff_in differential input voltage swing |in - /in| see figure 1b. 0.2 v v ref-ac reference voltage v cc ?1.3 v cc ?1.2 v cc ?1.1 v in-to-v t voltage from input to v t 1.8 v lvttl/cmos dc electri cal characteristics (5) v cc = 2.5v 5%; t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current ?125 30 a i il input low current ?300 a notes: 1. permanent device damage may occur if ratings in the ?absolute maximum ratings? sect ion are exceeded. this is a stress rating only and functional operation is not implied for condi tions other than those detailed in the operational sections of this datasheet. exposure to ab solute maximum ratings conditions for extended periods ma y affect device reliability. 2. the datasheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. due to the limited drive capability use for input of the same package only. 4. package thermal resistance assumes exposed pad is soldered (o r equivalent) to the device?s most negative potential on the pc b. jb uses 4-layer ja in still-air, unless otherwise stated. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 6. includes current through internal 50 ? pull-up.
micrel, inc. sy89200u april 2010 5 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 lvds output dc elect rical characteristics (7) v cc = 2.5v 5%; t a = ?40c to +85c; r l = 100 ? across q and /q, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage; (q, /q) 1.475 v v ol output low voltage; (q, /q) 0.925 v v out output voltage swing; (q, /q) 250 350 mv v diff_out differential output voltage swing |q ? /q| 500 700 mv v ocm output common mode voltage (q, /q) 1.125 1.275 v v ocm change in common mode voltage (q, /q) ?50 +50 mv ac electrical characteristics (8) v cc = 2.5v 5%; t a = ?40c to +85c; r l = 100 ? across all outputs (q and /q ), unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency v out >200mv clock 1.5 ghz in-to-q 500 700 900 ps t pd differential propagation delay /mr-to-q 900 ps t rr reset recovery time /mr(l-h)-to-(l-h) 900 ps t pd tempco differential propagation delay temperature coefficient 115 fs/c within-bank skew within same fanout bank, note 9 10 25 ps bank-to-bank skew same divide setting, note 10 15 35 ps bank-to-bank skew differential divide setting, note 10 25 50 ps t skew part-to-park skew note 11 200 ps random jitter (rj) note 12 1 ps rms total jitter (tj) note 13 10 ps pp t jitter cycle-to-cycle jitter note 14 1 ps rms t f , t f rise/fall time 20% to 80% at full output swing 40 80 150 ps notes: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 8. measured with 100mv input swing. see ?timing diagram? secti on for definition of parameters. high-frequency ac-parameters are guaranteed by design and characterization. 9. within-bank is the difference in propagation delays among the outputs within the same bank. 10. bank-to-bank skew is the difference in propagation delays bet ween outputs from difference banks. bank-to-bank skew is also the phase offset between each bank after mr is applied. 11. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. rj is measured with a k28.7 comma detect character pattern. 13. total jitter definition: with an ideal clock input of frequency f max , no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. 14. cycle-to-cycle jitter definition: the va riation of periods between adjacent cycles, t n ? t n-1 where t is the time between rising edges of the output signal.
micrel, inc. sy89200u april 2010 6 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 single-ended differential swings figure 1a. single-ended voltage swing figure 1b. differential voltage swing timing diagram figure 2a. reset with output enabled
micrel, inc. sy89200u april 2010 7 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 figure 2b. enable timing figure 2c. disable timing
micrel, inc. sy89200u april 2010 8 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics
micrel, inc. sy89200u april 2010 9 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 input stage internal termination figure 3. simplified differential input stage input interface applications figure 4a. cml interface (dc-coupled) figure 4b. cml interface (ac-coupled) figure 4c. lvpecl interface (dc-coupled) figure 4d. lvpecl interface (ac-coupled) figure 4e. lvds interface
micrel, inc. sy89200u april 2010 10 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 output interface applications lvds specifies a small swing of 350mv typical, on a nominal 1.25v common mode above ground. the common mode voltage has tight limits to permit large variations in ground between an lvds driver and receiver. also, change in common mode voltage, as a function of data input, is kept to a minimum to keep emi low. figure 5a. lvds differential measurement figure 5b. lvds common mode measurement related product and su pport documentation part number function datasheet link mlf ? application note www.amkor.com/pr oducts/notes_papers/ml f_appnote_0902.pdf hbw solutions new products and applications www.m icrel.com/product-info/products/solutions.shtml
micrel, inc. sy89200u april 2010 11 m9999-041210-f hbwhelp@micrel.com or (408) 955-1690 package information 32-pin micro leadframe ? (mlf-32) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2006 micrel, incorporated.

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